Description
- ND-100 CX CPU with 32 bit floating point.
- The ND-100 µprogram is stored in PROMs, arranged as 4K of 64 bits words.
- Using 4 pieces of the SRAM, 1024 x 4 bits x 4 pieces (total 2 KB).
- Print: B ECO: V
- Print: E ECO: V
- Print: S ECO: V
- PCB size 367 x 280 mm, 6 layers
- Release date xx. xxx. xxxx
Chipset
- 02600N
- 02601N
- 02602P
- 02603P
- 02604M
- 02805M
- 02606M
- 02607M
- 02608M
- 02609M
- 02610M
- 02611M
- 02612M
- 02613M
- 02614M
- 02615M
- 08500D
- 08501D
- 08502D
- 08503D
- 08504D
- 08505D
- 08506D
- 08507D
- 08508D
- 08509D
- 08510D
- 08511D
- 08512D
- 08513E
- 08514E
- 08515E
- 08600D
- 08601D
- 08602D
- AM2149 - SRAM x 4 pieces
- AM2901 - 4 bits microprocessor slice x 4 pieces
- AM2914 - Interrupt Controller x 2 pieces
- F4702 - Bit-rate generator x 2 pieces
- SN74482 - 4-bit slice control x 3 pieces
- IM6402 or
TR1863 - UART
LEDs
- LD4 (green) - Selftest passed
- LD3 (red) - Selftest failed
Straps
Switches
Connectors
- (A) Console and panel
- (B) Internal CPU/MMS bus
- (C) Standard ND-100 system bus
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Component side, PCB version B
Solder side, PCB version B
Component side, PCB version E
Solder side, PCB version E
Component side, PCB version S
Solder side, PCB version S
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