1.4.1.5 - Norsk Data hardware - ND-100

Description

• The Norsk Data 16 bits 110 CPU version II (rask), with CPU & MMS on one PCB board.
• Standard (Std) instruction set.
• 32 bits floating point arithmetic.
• Using 32 pieces of SRAM chips for the cache, 4096 x 4 bits x 32 pieces (total 64 KB).
• Using 17 pieces of SRAM chips for the control store, 4096 x 4 bits x 17 pieces (total 34 KB).
• Print: B   ECO: J
• PCB size 367 x 280 mm, 10 layers
• Release date 10. Aug. 1989

Chipset

• 37501B
• 37502A
• 37503A
• 37504C
• 37505C
• 37506C
• 37507B
• 37508A
• 37602E
• 37603A
• 37604C
• 37701B
• 37702B
• 37703B
• 37704C
• 37705A
• 37801F
• 37802A
• 37803A
• 37804B
• 37805C
• 37932L
• 37933L
• 43106C
• 43107B
• 43201B
• 44100A
• ND-BUFALU - the main CPU
• ND-RMAC
• ND-RMIC
• 74F403 or
  SN9403 - FIFO x 2 pieces
• AM2914 - Interrupt Controller x 2 pieces
• IM6402 - UART
• IMS1423 - SRAM x 49 pieces
• MM58274 - RTC

LEDs

• LED1 (green) - Selftest passed, microprogram running
• LED2 (red) - Selftest failed, selftest running
• LED3 (red) - Cache disabled, see switch in J21

Straps

• None

Switches

• SW1 (J30) - Master clear switch
• TH1 (J29) - ALD selector (Automatic Load Descriptor)
• SW2 (J21) - Cache disable switch
• TH2 (J9) - Console baudrate selector
• PT1 (J7) - Frequency adjustment for selftest oscillator (factory adjusted)

Connectors

• (A) Console and panel
• (B) Trace bus
• (C) Standard ND-100 system bus