1.4.1.7 - Norsk Data hardware - ND-500

Description

• Instruction Cache Controller in the ND-500/2 CPU.
• Maintains a 4K instruction cache with a 33 bits word size (27 bits segment address + 6 status bits).
• Using 33 pieces of SRAM chip for the cache memory, 4096 x 1 bit x 33 pieces (total 16.5 KB).
• Typical position is #8 in the ND-500/2 crate.
• Print: A   ECO: B
• PCB size 405 x 280 mm, 4 layers
• Release date xx. xxx. xxxx

Chipset

• 30700A
• 30701A
• CY7C147 or
  HM6147 - SRAM x 33 pieces

LEDs

• None

Straps

• None

Switches

• None

Connectors

• (A) Standard ND-500 bus
• (B) Standard ND-500 bus
• (C) Standard ND-500 bus
• (D) Standard ND-500 bus