1.4.1.7 - Norsk Data hardware - ND-500

Description

• Instruction cache module in the ND-500/2 CPU.
• Maintains 4K instruction cache with a 36 bits word size (32 bits word + 4 status bits).
• Using 36 pieces of SRAM chip for the cache memory, 4096 x 1 bit x 36 pieces (total 18 KB).
• Typical position is #7 in the ND-500/2 crate.
• Print: A   ECO: A
• PCB size 405 x 280 mm, 6 layers
• Release date xx. xxx. xxxx

Chipset

• 30600A
• 30601A
• 30602A
• CY7C147 or
  HM6147 - SRAM x 36 pieces

LEDs

• LD1 (yellow) - Enable for read data directly from cache (no alignment)
• LD2 (red) - Cache parity error detected
• LD3 (yellow) - Enable for read data from cache (aligned) or memory
• LD4 (yellow) - Not used
• LD5 (red) - Memory parity error detected
• LD6 (yellow) - Cache module selected

Straps

• None

Switches

• None

Connectors

• (A) Standard ND-500 bus
• (B) Standard ND-500 bus
• (C) Standard ND-500 bus
• (D) Standard ND-500 bus