1.4.1.7 - Norsk Data hardware - ND-500

Description

• Data Memory Management in the ND-500/2 CPU.
• Maintains the physical segment and capability tables.
• Using 18 pieces of SRAM chip for the MMS tables, 4096 x 4 bits x 18 pieces (total 36 KB).
• Using 2 pieces of SRAM chip, 4096 x 1 bit x 2 pieces (total 1 KB).
• On the PCB version Q; there are some ECOs done with very long wire ends on the solder side, this can not be right !
• Typical position is #12 in the ND-500/2 crate.
• Print: C   ECO: W
• Print: K   ECO: W
• Print: Q   ECO: W
• Print: U   ECO: W
• PCB size 405 x 280 mm, 4 layers
• Release date xx. xxx. xxxx

Chipset

• D2147 or
  HM6147 - SRAM x 2 pieces
• IMS1420 or
  IMS1421 or
  IMS1423 or
  TMM2068 - SRAM x 18 pieces

LEDs

• LD1 (yellow) - Memory management system on (paging on)

Straps

• None

Switches

• None

Connectors

• (A) Standard ND-500 bus
• (B) Standard ND-500 bus
• (C) Standard ND-500 bus
• (D) Standard ND-500 bus