Description
- The memory channel driver in the ND-500/2 CPU.
- Print: A ECO: E
- PCB size 405 x 280 mm, 4 layers
- Release date xx. xxx. xxxx
Chipset
LEDs
- LED 1 (yellow) - Enable for read data directly from cache (no alignment)
- LED 2 (red) - Cache parity error detected
- LED 3 (yellow) - Enable for read data from cache (aligned) or memory
- LED 4 (yellow) - Not used
- LED 5 (red) - Memory parity error detected
- LED 6 (yellow) - Cache module selected
Straps
Switches
Connectors
- (A) Standard ND-500 bus
- (B) Standard ND-500 bus
- (C) Standard ND-500 bus
- (D) Standard ND-500 bus
|
Component side, PCB version A
Solder side, PCB version A
|