1.4.1.7 - Norsk Data hardware - ND-500

Description

• The Memory Management System (MMS 2) in the ND-500/1 CPU.
• Maintains the physical segment and capability tables.
• Using 8 pieces of SRAM chip for the MMS tables, 4096 x 1 bit x 8 pieces (total 4 KB).
• Using 14 pieces of SRAM chip for the MMS tables, 1024 x 4 bits x 14 pieces (total 7 KB).
• Print: B   ECO: L
• Print: E   ECO: L
• PCB size 405 x 280 mm, 4 layers
• Release date xx. xxx. xxxx

Chipset

• HM6147 or
  MCM6147 - SRAM x 8 pieces
• AM2148 or
  D/P2148 - SRAM x 14 pieces
• SN74154 - Decoders/Demultiplexers x 2 pieces

LEDs

• LD1 (yellow) - Memory management system on (paging on)

Straps

• None

Switches

• None

Connectors

• (A) Standard ND-500 bus
• (B) Standard ND-500 bus
• (C) Standard ND-500 bus
• (D) Standard ND-500 bus