1.4.1.7 - Norsk Data hardware - ND-500

Description

• Data or Instruction cache controller in the ND-500/1 CPU.
• The cards have an interesting ECO in the upper left corner (ECO level T, ECO no. 146 - Marginal timing when read status after cache clear. Symptom: Failing in cache clear test in GMENT).
  When the W (Write Enable signal) goes from low to high, the low Ea (Enable input a on the SN74S139) will be stretched with a few ns before going high, just enough for the read status to be completed. The original direct track from W to Ea is cut on the solder side of the PCB.
• Maintains a 4K of 27 bits width logical segment address directory by using static RAM chips, 4096 x 1 bit x 27 pieces (total 13.5 KB).
• Contains 4 PROMs with instruction cache logic, 32 x 8 bits x 4 pieces (total 128 bytes).
• The PCB version E has a lot of ECO wiring
• Print: E   ECO: U
• Print: G   ECO: U
• Print: L   ECO: U
• Print: P   ECO: U
• PCB size 405 x 280 mm, 4 layers
• Release date xx. xxx. xxxx

Chipset

• 05100A
• 05101A
• 05102A
• 05103A
• D2147 or
  HM6147 or
  SY2147 - SRAM x 27 pieces
• SN74S288 - PROM x 4 pieces

LEDs

• None

Straps

• None

Switches

• None

Connectors

• (A) Standard ND-500 bus
• (B) Standard ND-500 bus
• (C) Standard ND-500 bus
• (D) Standard ND-500 bus