1.4.1.7 - Norsk Data hardware - ND-500

Description

• Data or Instruction cache module in the ND-500/1 CPU.
• Maintains 4K cached data/instruction words of 36 bits each (a 32 bits word + 4 status bits)
• Using 36 pieces of SRAM chips for the cache, 4096 x 1 bit x 36 pieces (total 18 KB).
• Print: A   ECO: D
• PCB size 405 x 280 mm, 4 layers
• Release date xx. xxx. xxxx

Chipset

• 03200A
• 03201A
• 03202A
• 03203A
• 03204A
• HM6147 or
  MCM6147 - SRAM x 36 pieces

LEDs

• LED 1 (yellow) - Enable for read data directly from cache (no alignment)
• LED 2 (yellow) - Cache parity error detected
• LED 3 (yellow) - Enable for read data from cache (aligned) or memory
• LED 4 (yellow) - Not used
• LED 5 (red) - Memory parity error detected
• LED 6 (yellow) - Cache module selected

Straps

• None

Switches

• None

Connectors

• (A) Standard ND-500 bus
• (B) Standard ND-500 bus
• (C) Standard ND-500 bus
• (D) Standard ND-500 bus