Description
- The Memory Management System (MMS 1) in the ND-500/1 CPU.
- Maintains the physical segment and capability tables.
- Using 8 pieces of SRAM chip for the MMS tables, 4096 x 1 bit x 8 pieces (total 4 KB).
- Using 14 pieces of SRAM chip for the MMS tables, 1024 x 4 bits x 14 pieces (total 7 KB).
- Print: D ECO: U
- PCB size 405 x 280 mm, 4 layers
- Release date xx. xxx. xxxx
Chipset
- D2147 - SRAM x 8 pieces
- D2148 - SRAM x 14 pieces
- SN74154 - Decoders/Demultiplexers x 2 pieces
LEDs
- LD1 (yellow) - Memory management system on (paging on)
Straps
Switches
Connectors
- (A) Standard ND-500 bus
- (B) Standard ND-500 bus
- (C) Standard ND-500 bus
- (D) Standard ND-500 bus
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Component side, PCB version D
Solder side, PCB version D
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