1.4.1.5 - Norsk Data hardware - ND-100

Description

• ND-120 CPU with 32 bit floating point and 6MB on board memory.
• Using 6 pieces of the 9 bits DRAM modules, 1048576 x 9 bits x 6 pieces (total 6.75 MB).
• Using 10 pieces of the SRAM modules for internal memory, 2048 x 8 bits x 10 pieces (total 20 KB).
• Using 32 pieces of SRAM chips for the cache, 4096 x 4 bits x 32 pieces (total 64 KB).
• Using an onboard RTC (Real Time Clock) with battery backup.
• Print: C   ECO: P
• Print: D   ECO: P
• PCB size 367 x 280 mm, 10 layers
• Release date 05. Mar. 1990

Chipset

• 44100A
• 44302B
• 44303B
• 44304F
• 44305D
• 44306A
• 44307C
• 44310D
• 44401B
• 44403D
• 44404D
• 44407A
• 44412A
• 44465B
• 44466B
• 44511A
• 44608A
• 44611A
• 44801A
• 44803A
• 44902B
• 44904B
• 45001C
• 45008B
• 45009B
• 45132L
• 45133L
• DEL CGA - the main CPU, Delilah customer gate array
• ND-DGA
• THM91020 - DRAM x 6 pieces
• SCN2661 - EPCI
• HM65768 or
  IMS1423 - SRAM x 32 pieces
• MM58274 - RTC
• TMM2018 - SRAM x 10 pieces

LEDs

• LED3 (green) - Selftest passed
• LED2 (red) - Selftest failed
• LED1 (red) - Cache disabled
• LED6 (green) - CPU grant
• LED7 (yellow) - Bus grant
• LED4 (red) - Parity error detected
• LED5 (red) - Parity error disabled
• Memory upper limit display

Straps

• STR1, STR16-18 (H29) - Internal data bus to B connector
• STR5-9 (A30) - ECO level
• STR13-15 (G26) -
• STR19 (F10) -
• STR20 (B30) - Chargeable clock battery installed

Switches

• SW3 - Master clear
• TH1 - ALD selector
• TH2 - Console baudrate selector
• SW1 - Cache disable switch
• SW2 - Local memory disable switch
• SW4 - Parity error detection disable switch

Connectors

• (A) Console and panel
• (B) Trace bus
• (C) Standard ND-100 system bus