Description
- Ethernet interface version II, 10Mb LANCE.
- Using 18 pieces of DRAM chips for local memory (8 bits words + 1 parity bit), 262144 x 1 bit x 18 pieces (total 576 KB).
- Print: B ECO: M
- Print: C ECO: M
- Print: E ECO: M
- Print: G ECO: M
- PCB size 367 x 280 mm, 4 layers
- Release date 27. Mar. 1989
Chipset
LEDs
- EXT-POWER (yellow) - tranceiver power on
- MCYC (yellow) - active memory cycle
- HALT (red) - MC68000 halt
- RESET (red) - MC68000 reset
- PARITY-ERROR (red) - parity error
Straps
Switches
- TH1 - Device number
- TH2 - Bank, (L) lower limit memory address switch
- TH3 - Bank, (M) lower limit memory address switch
Connectors
- J13 - Console/Trace terminal
- (A) Ethernet drop cable
- (B) Not used
- (C) Standard ND-100 system bus
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Component side, PCB version B
Solder side, PCB version B
Component side, PCB version C
Solder side, PCB version C
Component side, PCB version E
Solder side, PCB version E
Component side, PCB version G
Solder side, PCB version G
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