1.4.1.5 - Norsk Data hardware - ND-100

Description

• The MMS and data/instruction cache for the ND-100 CPU.
• Using the P8254 as the calendar.
• One of the PCBs (version G) has been used for educational purposes, where a lot of the MMS function blocks are marked.
• Using 17 piece of RAM chips for the cache, 1024 x 4 bits x 17 pieces (total 8.5 KB).
• The 8156 chip also have a little RAM, 256 x 8 bits x 1 pieces (total 256 bytes).
• Print: B   ECO: G
• Print: E   ECO: G
• Print: G   ECO: G
• PCB size 367 x 280 mm, 4 layers
• Release date xx. xxx. xxxx

Chipset

• 01100A
• 9403 - FIFO buffer x 2 pieces
• D2149 - RAM x 17 pieces
• D8253 or
  D8254 or
  P8253 or
  P8254 - Programmable timer
• P8085 or
  TMP8085 - MPU
• M5L8156 or
  TMP8156 - SRAM, IO ports and Timer

LEDs

• LD1 (red) - Cache disable indictor

Straps

• None

Switches

• SW1 (J6) - Cache disable switch

Connectors

• (A) Console and panel
• (B) Internal CPU/MMS bus
• (C) Standard ND-100 system bus