Description
- 2 MB with dynamic memory for the ND-100 crate.
- Arranged as 22 bits words (16 bits ND-100 word (or 2 bytes) + 6 bits ECC).
- Using 88 pieces of DRAM chip for the memory, 262144 x 1 bit x 88 pieces (total 2.75 MB).
- Print: A ECO: D
- Print: B ECO: D
- PCB size 367 x 280 mm, 4 layers
- Release date xx. xxx. xxxx
Chipset
LEDs
- Upper limit display
- LD6 (yellow) - 1½-2 MB active
- LD5 (yellow) - 1-½ MB active
- LD4 (yellow) - ½-1 MB active
- LD3 (yellow) - 0-½ MB active
- LD2 (red) - ERROR - memory error
- LD1 (red) - DISABLE - ECC disabled
Straps
Switches
- TH1 - Lower limit memory address
- TH2 - Lower limit memory address
- TH3 - Lower limit memory address
- SW1 - ECC disable switch
Connectors
- (A) Dummy
- (B) Not present
- (C) Standard ND-100 system bus
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Component side, PCB version A, D41256
Solder side, PCB version A, D41256
Component side, PCB version A, HM50256
Solder side, PCB version A, HM50256
Component side, PCB version A, TMM41256 replacements
Solder side, PCB version A, TMM41256 replacements
Component side, PCB version B, D41256
Solder side, PCB version B, D41256
Component side, PCB version B, HM50256
Solder side, PCB version B, HM50256
Component side, PCB version B, HM51256
Solder side, PCB version B, HM51256
Component side, PCB version B, HYB41256
Solder side, PCB version B, HYB41256
Component side, PCB version B, TMM41256
Solder side, PCB version B, TMM41256
Component side, PCB version B, TMS4256
Solder side, PCB version B, TMS4256
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